Processing often includes the movement of data. Such data movement often occurs between elements having data storage, both permanent and temporary. Such movement can be within a processor, between processors with onboard (on-chip) storage, between a processor and memory not located on-chip (such as off-chip DRAM), or otherwise. These transfers happen over a “bus” which is a subsystem that transfers data between components. Busses have “widths” that define how many bits of data can be sent at a time. Common bus widths provide for 16, 32, and 64 bits (powers of 2 generally, although other sizes can and have been used) to be communicated in a single clock pulse. Data to be sent over these busses is thus grouped into 16, 32, or 64 bits, as appropriate. These groupings are referred to as “words.”
Regardless of the source and destination of the transfer, such transfers require power. For many of the transfers, the power that is needed is directly related to the number of bits that need to be toggled between successively transmitted data words. Values to be sent across a bus are often established in a register that receives a clock signal. The clock signal then causes the register to output its current state as the transmitted word. Many transmission registers include the use of capacitors. Changing a bit value in the register often involves at least partial discharge of energy from a respective capacitor. That capacitor subsequently needs to be recharged, thereby drawing power. Thus, reduced bit toggling results in reduced power consumption.
Data transfer is often performed using first-in, first-out (FIFO) buffers at the transmission end and reception end. Thus, words are transmitted in the order that they are received and differences between successive words thus cause toggling and power draws.
To lessen the amount of bit toggling, concepts such as bus inversion and signal change encoding have been developed. Bus inversion causes a bit to be provided that indicates that a sent data word is actually the opposite of what is intended. Thus, the receiving entity knows to actually write the opposite value for each received bit. For any data word where greater than 50% of the bits change relative to the previously sent data word, data inversion likely reduces the toggling required.
Similarly, the concept of signal encoding operates to lessen the toggling of bits. For bits that are known to change often, a receiving entity can interpret a high signal (“1”) as an instruction to use the inverse of the bit's value in the previously received word. The receiving entity interprets a low signal (“0”) as an instruction to reuse the value of the bit from the previous word. Accordingly, for a bit that fluctuates with each clock segment, the communicating bit can remain high on the bus and the receiving entity knows that the proper value is fluctuating with each clock pulse. Again, signal encoding of this type would be expected to provide power savings when the bit is expected to change between successive words over 50% of the time.
Despite these techniques, bit toggling in data busses continues to be a source of power consumption. Accordingly, there exists a need for additional power savings associated with the transfer of data over busses.